Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
Language
EN
Communication dans un congrès avec actes
This item was published in
30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), 2022-10-03, Patras. 2022-11-08
IEEE
English Abstract
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the ...Read more >
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.Read less <
English Keywords
Semiconductor device modeling
Solid modeling
Three-dimensional displays
Integrated circuit interconnections
Very large scale integration
SPICE
Inverters
Junction-less nanowire transistors
3D logic cells
Compact model
TCAD simulation
Parasitic interconnects
ANR Project
Portes logiques élémentaires empillées - ANR-18-CE24-0005