Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
Langue
EN
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Ce document a été publié dans
30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), 2022-10-03, Patras. 2022-11-08
IEEE
Résumé en anglais
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the ...Lire la suite >
Mots clés en anglais
Semiconductor device modeling
Solid modeling
Three-dimensional displays
Integrated circuit interconnections
Very large scale integration
SPICE
Inverters
Junction-less nanowire transistors
3D logic cells
Compact model
TCAD simulation
Parasitic interconnects
Project ANR
Portes logiques élémentaires empillées - ANR-18-CE24-0005