Circuit Design Flow dedicated to 3D vertical nanowire FET
Language
EN
Communication dans un congrès avec actes
This item was published in
IEEE Latin American Electron Devices Conference (LAEDC 2022), IEEE Latin American Electron Devices Conference (LAEDC 2022), 2022-07-04, Cancun. 2022-10-10
IEEE
English Abstract
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit ...Read more >
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored.Read less <
English Keywords
Solid modeling
Three-dimensional displays
Logic circuits
Field effect transistors
Logic gates
Nanoscale devices
Circuit synthesis
Compact modelling
DC characterization
Parasitics extraction
EM simulation
VNWFET
3D logic circuit simulation
ANR Project
Portes logiques élémentaires empillées - ANR-18-CE24-0005