Circuit Design Flow dedicated to 3D vertical nanowire FET
| dc.rights.license | open | en_US |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MANEUX, Cristell
IDREF: 135213584 | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MUKHERJEE, Chhandak
IDREF: 228231779 | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | DENG, Marina
IDREF: 184622409 | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | NECKEL WESLING, Bruno | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | REVEIL, Lucas | |
| dc.contributor.author | STANOJEVIC, Zlatan | |
| dc.contributor.author | BAUMGARTNER, Oskar | |
| dc.contributor.author | O'CONNOR, Ian | |
| dc.contributor.author | POITTEVIN, Arnaud | |
| dc.contributor.author | LARRIEU, Guilhem | |
| dc.date.accessioned | 2023-02-03T15:27:52Z | |
| dc.date.available | 2023-02-03T15:27:52Z | |
| dc.date.issued | 2022-10-10 | |
| dc.date.conference | 2022-07-04 | |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/171865 | |
| dc.description.abstractEn | To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored. | |
| dc.description.sponsorship | Portes logiques élémentaires empillées - ANR-18-CE24-0005 | en_US |
| dc.language.iso | EN | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject.en | Solid modeling | |
| dc.subject.en | Three-dimensional displays | |
| dc.subject.en | Logic circuits | |
| dc.subject.en | Field effect transistors | |
| dc.subject.en | Logic gates | |
| dc.subject.en | Nanoscale devices | |
| dc.subject.en | Circuit synthesis | |
| dc.subject.en | Compact modelling | |
| dc.subject.en | DC characterization | |
| dc.subject.en | Parasitics extraction | |
| dc.subject.en | EM simulation | |
| dc.subject.en | VNWFET | |
| dc.subject.en | 3D logic circuit simulation | |
| dc.title.en | Circuit Design Flow dedicated to 3D vertical nanowire FET | |
| dc.type | Communication dans un congrès avec actes | en_US |
| dc.identifier.doi | 10.1109/LAEDC54796.2022.9908233 | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics] | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics]/Electronique | en_US |
| bordeaux.hal.laboratories | IMS : Laboratoire d’Intégration du Matériau au Système - UMR 5218 | en_US |
| bordeaux.institution | Université de Bordeaux | en_US |
| bordeaux.institution | Bordeaux INP | en_US |
| bordeaux.institution | CNRS | en_US |
| bordeaux.conference.title | IEEE Latin American Electron Devices Conference (LAEDC 2022) | en_US |
| bordeaux.country | mx | en_US |
| bordeaux.title.proceeding | IEEE Latin American Electron Devices Conference (LAEDC 2022) | en_US |
| bordeaux.conference.city | Cancun | en_US |
| bordeaux.peerReviewed | oui | en_US |
| bordeaux.import.source | hal | |
| hal.identifier | hal-03765071 | |
| hal.version | 1 | |
| hal.export | false | |
| workflow.import.source | hal | |
| dc.rights.cc | Pas de Licence CC | en_US |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-10-10&rft.au=MANEUX,%20Cristell&MUKHERJEE,%20Chhandak&DENG,%20Marina&NECKEL%20WESLING,%20Bruno&REVEIL,%20Lucas&rft.genre=proceeding |
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