Circuit Design Flow dedicated to 3D vertical nanowire FET
Idioma
EN
Communication dans un congrès avec actes
Este ítem está publicado en
IEEE Latin American Electron Devices Conference (LAEDC 2022), IEEE Latin American Electron Devices Conference (LAEDC 2022), 2022-07-04, Cancun. 2022-10-10
IEEE
Resumen en inglés
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit ...Leer más >
Palabras clave en inglés
Solid modeling
Three-dimensional displays
Logic circuits
Field effect transistors
Logic gates
Nanoscale devices
Circuit synthesis
Compact modelling
DC characterization
Parasitics extraction
EM simulation
VNWFET
3D logic circuit simulation
Proyecto ANR
Portes logiques élémentaires empillées - ANR-18-CE24-0005