Since the first generation of mobile phones, a lot of functions, standards and tools have been integrated on handsets. Twenty years ago, consumers could use their mobile phones only to call and to send messages. Nowadays, ...
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Since the first generation of mobile phones, a lot of functions, standards and tools have been integrated on handsets. Twenty years ago, consumers could use their mobile phones only to call and to send messages. Nowadays, internet access, radio, cameras, games and music are included and available as options for every mobile phone.All of these new services make the cost of production for a cellular phone more expensive. Despite that, industry has to find a solution to maintain their products the most attractive as possible including the large range of integrated functions.In the context of interaction with other standards, the aim of this thesis is to design and implement a chipset able to improve the linearity of a transmitter for third generation mobile phones, using both digital and analog technologies. For this purpose, the study will focus on the improvement of the linearity, keeping the consumption and the die area of the circuit as small as possible. We will prove that linearization on an integrated circuit is possible with almost the same consumption and die area occupation compared to a classic transmitter.The first chapter presents the different architectures used for a transmitter and various linearization techniques with their advantages and drawbacks. Some metrics are also presented in order to evaluate these architectures. The goal of this part is to choose a linearization technique associated to a transmitter in order to fit with our application and constraints.The second chapter explains the complete system, digital and analog parts, with theoretical studies. We will start by detailing the constraints and precautions that must be taken into account by the designer to study the instability and the noise generated by the transmitter. We will describe how two algorithms make signal corrections. In the last part we will show system level simulations of the Cartesian Feedback using, first, an ideal power amplifier (PA), then, a PA in a BiCMOS technology, and finally, a PA in a CMOS technology that will be used for the final integrated circuit.The third and last chapter shows the digital synthesis in a CMOS technology of the two algorithms previously mentioned, considering all steps, from the VHDL code until the layout of the digital part. We will describe and simulate each analog building block of the Cartesian Feedback, with the measurement results for some of them. Each chapter will be working towards the goal of this study, demonstrated in this part: to make an integrated system, with its complete solution and simulations.This chapter presents the integration of the analog and digital Cartesian Feedback described previously in 65nm CMOS technology from STMicroelectronics. First, the digital part generating the phase correction and subtraction will be shown in ASIC technology, with a CORDIC algorithm to reduce its consumption and size. Secondly, the architecture and specification of building blocks will be shown. In our case, the direct path is composed of filters, RF modulator and a Power Amplifier. Our objective is to design these three functions to minimize the consumption and the silicon area of the integrated architecture. Finally, system level simulations will be presented using the ADS (Advanced Design Software) from Agilent for the analog part. Co-simulations have been done to analyze the whole system, with SystemVue for the digital part. The simulations using ADS will provide the performance of each building block on the transistors level.
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