LE GAL, Bertrand; PIGNOLY, Vincent; JEGO, Christophe

doi:10.1007/978-3-031-12748-9_1

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LE GAL, Bertrand
Laboratoire de l'intégration, du matériau au système [IMS]

PIGNOLY, Vincent

Laboratoire de l'intégration, du matériau au système [IMS]

JEGO, Christophe
Laboratoire de l'intégration, du matériau au système [IMS]

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Communication dans un congrès avec actes

Ce document a été publié dans

Design and Architecture for Signal and Image Processing, 15th International Workshop, DASIP 2022 Budapest, Hungary, June 20-22, 2022, Proceedings, 2022-06-20, Budapest. 2022-07-30, vol. 13425, p. 3-15

Résumé en anglais

LDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multi-core devices facilitate real-time implementations of digital communication systems, which were previously implemented thanks to dedicated hardware circuits. A lot of works were done over the last decade on the implementation of Gbps decoders on programmable devices. However, these works focus on soft-input LDPC decoding algorithms. But, hard-input LDPC decoders are also required to design and prototype optical-based satellite communication systems. In this article, the first software based implementation of a hard-input multi-Gbps LDPC decoder is detailed. Thanks to different parallelization strategies and deeply optimized SIMD codes, throughputs up to 7.5 Gbps are achieved when 10 Gallager-E iterations are executed onto an INTEL Xeon device.< Réduire

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LDPC

Gallager E

Multi-core

SIMD

High-throughput

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High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices

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