High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices
| dc.rights.license | open | en_US |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | LE GAL, Bertrand | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | PIGNOLY, Vincent | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | JEGO, Christophe | |
| dc.contributor.editor | DESNOS, Karol | |
| dc.contributor.editor | PERTUZ, Sergio | |
| dc.date.accessioned | 2023-05-23T08:55:25Z | |
| dc.date.available | 2023-05-23T08:55:25Z | |
| dc.date.issued | 2022-07-30 | |
| dc.date.conference | 2022-06-20 | |
| dc.identifier.issn | 1611-3349 | en_US |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/182255 | |
| dc.description.abstractEn | LDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multi-core devices facilitate real-time implementations of digital communication systems, which were previously implemented thanks to dedicated hardware circuits. A lot of works were done over the last decade on the implementation of Gbps decoders on programmable devices. However, these works focus on soft-input LDPC decoding algorithms. But, hard-input LDPC decoders are also required to design and prototype optical-based satellite communication systems. In this article, the first software based implementation of a hard-input multi-Gbps LDPC decoder is detailed. Thanks to different parallelization strategies and deeply optimized SIMD codes, throughputs up to 7.5 Gbps are achieved when 10 Gallager-E iterations are executed onto an INTEL Xeon device. | |
| dc.language.iso | EN | en_US |
| dc.subject | LDPC | |
| dc.subject | Gallager E | |
| dc.subject | Multi-core | |
| dc.subject | SIMD | |
| dc.subject | High-throughput | |
| dc.title.en | High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices | |
| dc.type | Communication dans un congrès avec actes | en_US |
| dc.identifier.doi | 10.1007/978-3-031-12748-9_1 | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics] | en_US |
| bordeaux.page | 3-15 | en_US |
| bordeaux.volume | 13425 | en_US |
| bordeaux.hal.laboratories | IMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218 | en_US |
| bordeaux.institution | Université de Bordeaux | en_US |
| bordeaux.institution | Bordeaux INP | en_US |
| bordeaux.institution | CNRS | en_US |
| bordeaux.conference.title | 15th International Workshop, DASIP 2022 Budapest, Hungary, June 20-22, 2022, Proceedings | en_US |
| bordeaux.country | hu | en_US |
| bordeaux.title.proceeding | Design and Architecture for Signal and Image Processing | en_US |
| bordeaux.team | CONCEPTION-CSN | en_US |
| bordeaux.conference.city | Budapest | en_US |
| bordeaux.peerReviewed | oui | en_US |
| hal.identifier | hal-04103371 | |
| hal.version | 1 | |
| hal.date.transferred | 2023-05-23T08:55:27Z | |
| hal.export | true | |
| dc.rights.cc | Pas de Licence CC | en_US |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-07-30&rft.volume=13425&rft.spage=3-15&rft.epage=3-15&rft.eissn=1611-3349&rft.issn=1611-3349&rft.au=LE%20GAL,%20Bertrand&PIGNOLY,%20Vincent&JEGO,%20Christophe&rft.genre=proceeding |
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