Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor
Langue
EN
Article de revue
Ce document a été publié dans
Solid-State Electronics. 2022-08, vol. 194, p. 108359
Résumé en anglais
In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology ...Lire la suite >
In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic smallsignal parameters such as the gate capacitances.< Réduire
Mots clés en anglais
Test structure
Equivalent circuit
Parasitic components
RF measurements
De-embedding
Unités de recherche