A DEVS-based pivotal modeling formalism and its verification and validation framework
Language
EN
Article de revue
This item was published in
SIMULATION. 2020-09-26, vol. 96, n° 12, p. 969-992
English Abstract
System verification is an ever-lasting system engineering challenge. The increasing complexity in system simulation requires some level of expertise in handling the idioms of logic and discrete mathematics to correctly ...Read more >
System verification is an ever-lasting system engineering challenge. The increasing complexity in system simulation requires some level of expertise in handling the idioms of logic and discrete mathematics to correctly drive a full verification process. It is recognized that visual modeling can help to fill the knowledge gap between system experts and analysis experts. However, such an approach has been used on the one hand to specify the behavior of complex systems, and on the other hand to specify complex requirement properties, but not simultaneously. This paper proposes a framework that is unique in supporting a full system verification process based on the graphical modeling of both the system of interest and the requirements to be checked. Patterns are defined to transform the resulting models to formal specifications that a model checker can manipulate. A real-time crossing system is used to illustrate the proposed framework.Read less <
English Keywords
High Level Language for Systems Specification (HiLLS)
Discrete Event System Specification (DEVS)
formal verification
temporal logic
model transformation
UPPAAL