High-throughput FFT architectures using HLS tools
Idioma
EN
Communication dans un congrès
Este ítem está publicado en
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2022-10-24, Glasgow. 2022-10p. 1-4
Resumen en inglés
High-Level Synthesis (HLS) tools are an attractive option for fast prototyping and implementation of hardware accelerators performing digital signal processing algorithms such as the Fast Fourier Transform (FFT). However, ...Leer más >
High-Level Synthesis (HLS) tools are an attractive option for fast prototyping and implementation of hardware accelerators performing digital signal processing algorithms such as the Fast Fourier Transform (FFT). However, the efficiency and the performance level of the generated architectures depend on the behavioral models. Moreover, Design Space Exploration features enabled by HLS tools are limited by the behavioral model parallelization features. In this paper, a generic FFT behavioral model usable within HLS tools is presented. Its configurable parameters enable to cover a broader architectural space by taking advantage of more parallelization strategies contrary of related works. Thus, this designed model can produce low-complexity architectures up to high throughput ones as highlighted by experimental results.< Leer menos
Palabras clave
Fast Fourier transforms
Signal processing algorithms
Digital signal processing
Licenses
Throughput
Behavioral sciences
Space exploration
FFT
Digital architecture
FPGA
HLS
Model
Centros de investigación