ALMORIN, Hugues; LE GAL, Bertrand; CRENNE, Jeremie; JEGO, Christophe; KISSEL, Vincent

doi:10.1109/ICECS202256217.2022.9970886

Métadonnées

Afficher la notice complète

Licence d’utilisation du document

ALMORIN, Hugues
Laboratoire de l'intégration, du matériau au système [IMS]

LE GAL, Bertrand
Laboratoire de l'intégration, du matériau au système [IMS]

CRENNE, Jeremie
Laboratoire de l'intégration, du matériau au système [IMS]

Langue

Communication dans un congrès

Ce document a été publié dans

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2022-10-24, Glasgow. 2022-10p. 1-4

Résumé en anglais

High-Level Synthesis (HLS) tools are an attractive option for fast prototyping and implementation of hardware accelerators performing digital signal processing algorithms such as the Fast Fourier Transform (FFT). However, the efficiency and the performance level of the generated architectures depend on the behavioral models. Moreover, Design Space Exploration features enabled by HLS tools are limited by the behavioral model parallelization features. In this paper, a generic FFT behavioral model usable within HLS tools is presented. Its configurable parameters enable to cover a broader architectural space by taking advantage of more parallelization strategies contrary of related works. Thus, this designed model can produce low-complexity architectures up to high throughput ones as highlighted by experimental results.< Réduire

Mots clés

Fast Fourier transforms

Signal processing algorithms

Digital signal processing

Licenses

Throughput

Behavioral sciences

Space exploration

FFT

Digital architecture

FPGA

HLS

Model

Métadonnées

Partager cette publication !

Licence d’utilisation du document

High-throughput FFT architectures using HLS tools

Langue

Ce document a été publié dans

Résumé en anglais

Mots clés

URI

DOI

Unités de recherche