MBSPDiscover: An Automatic Benchmark for MultiBSP Performance Analysis
ALANIZ, Marcelo
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
GOGLIN, Brice
Efficient runtime systems for parallel architectures [RUNTIME]
Laboratoire Bordelais de Recherche en Informatique [LaBRI]
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Efficient runtime systems for parallel architectures [RUNTIME]
Laboratoire Bordelais de Recherche en Informatique [LaBRI]
ALANIZ, Marcelo
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
GOGLIN, Brice
Efficient runtime systems for parallel architectures [RUNTIME]
Laboratoire Bordelais de Recherche en Informatique [LaBRI]
Efficient runtime systems for parallel architectures [RUNTIME]
Laboratoire Bordelais de Recherche en Informatique [LaBRI]
GIL COSTA, Veronica
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
PRINTISTA, Marcela
Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
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Laboratorio de Investigación y Desarrollo en Inteligencia Computacional [San Luis] [LIDIC]
Langue
en
Communication dans un congrès
Ce document a été publié dans
First HPCLATAM - CLCAR Joint Latin American High Performance Computing Conference, 2014-10-20, Valparaiso. 2014-10-20, vol. 485, p. 158-172
Springer
Résumé en anglais
Multi-Bulk Synchronous Parallel (MultiBSP) is a recently proposed parallel programming model for multicore machines that extends the classic BSP model. MultiBSP is very useful to design algorithms and estimate their running ...Lire la suite >
Multi-Bulk Synchronous Parallel (MultiBSP) is a recently proposed parallel programming model for multicore machines that extends the classic BSP model. MultiBSP is very useful to design algorithms and estimate their running time, which are hard to do in High Performance Computing applications. For a correct estimation of the running time, the main parameters of the MultiBSP model for different multicore architectures need to be determined. This article presents a benchmark proposal for measuring the parameters that characterize the communication and synchronization cost for the model. Our approach discovers automatically the hierarchical structure of the multicore architecture by using a specific tool (hwloc) that allows obtaining runtime information about the machine. We describe the design, implementation and the results of benchmarking two multicore machines. Furthermore, we report the validation of the proposed method by using a real MultiBSP implementation of the vector inner product algorithm and comparing the predicted execution time against the real execution time.< Réduire
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