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This is not the latest version of this item. The latest version can be found at: https://oskar-bordeaux.fr/handle/20.500.12278/173667.2
Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology
Language
EN
Communication dans un congrès avec actes
This item was published in
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 2022-03-01, Puerto Varas. 2022-06-08p. 1-4
Abstract
In this work, Integer N frequency dividers are designed in a dual loop PLL circuit which is applicable at reference frequency 40.92MHz and 400MHz and for a feedback input frequency 0.8GHz-6.3GHz with very low power consumption ...Read more >
Keywords
Phase noise
Frequency locked loops
Power demand
Circuits and systems
Silicon-on-insulator
Frequency conversion
Energy efficiency
Clocks
Flip-flops
Frequency dividers
Low-power electronics
Phase locked loops
Phase noise
Silicon-on-insulator
TSPC
FDSOI
Drequency dividers
De-counter
Phase noise
European Project
Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node