A Logic Cell Design and routing Methodology Specific to VNWFET
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EN
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Este ítem está publicado en
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 2022-06-19, Quebec City. 2022-08-05p. 460-464
IEEE
Resumen en inglés
New emerging Vertical NanoWire Field-E昀昀ect Transistors (VNWFET) appear promising for compact energy e昀케cient computing architectures, still, we notice a lack of technology aware and coherent design methodologies. Such ...Leer más >
New emerging Vertical NanoWire Field-E昀昀ect Transistors (VNWFET) appear promising for compact energy e昀케cient computing architectures, still, we notice a lack of technology aware and coherent design methodologies. Such tools would enable a thorough exploration of the bene昀椀ts of these new technologies at the circuit level. This paper explores a complete methodology for designing a logic cell library using VNWFET. The methodology includes low-level logic cells Technology Computer Aided Design (TCAD) simulations, Parasitic Extraction (PEX) of predictive devices and 3D physical design rules and cell generation. In this design method, we focus on the standard CMOS logic cells, with up to 12 transistors and detail the inter-transistor routing. The various cells generated using this method are tested using TCAD and selected based on their PEX results. The whole process is performed on logic cell examples and in the light of the current design context, results show an improvement in footprint area optimization.< Leer menos
Palabras clave en inglés
VNWFET
junction-less
logic cell
routing
predictive
simulation
technology
TCAD
Manhattan
Proyecto ANR
Portes logiques élémentaires empillées - ANR-18-CE24-0005
Centros de investigación