GAIDIOZ, David; CATHELIN, Andreia; DEVAL, Yann

doi:10.1109/tmtt.2022.3149826

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GAIDIOZ, David

CATHELIN, Andreia

DEVAL, Yann
Laboratoire de l'intégration, du matériau au système [IMS]

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IEEE Transactions on Microwave Theory and Techniques. 2022-04, vol. 70, n° 4, p. 2207-2216

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This article presents a 2.4-GHz low-power compact integer- N ring oscillator-based phase-locked loop (PLL) for Internet of Things (IoT) applications. The proposed integer- N PLL is based on a dual loop Offset-PLL topology to achieve a fine frequency resolution similar to conventional fractional- N PLL. Not using a delta-sigma modulator (DSM) allows an expanded PLL bandwidth without deteriorating the overall noise performance. Implemented in 28 nm CMOS fully depleted silicon on insulator (FD-SOI) technology, the proposed architecture requires a 22-MHz internal reference frequency while achieving a 2-MHz frequency resolution and a 3-MHz PLL bandwidth. Measured prototypes perform −43.9 dBc reference spur, as an average value over all the bluetooth low energy (BLE) band and numerous tested dies, a jitter Figure-of-Merit of −229.6 dB for a power consumption of 0.87 mW and a core area of 0.0256 mm2.< Réduire

Mots clés en anglais

Dual-loop phase-locked loop (PLL) architecture

Internet of Things (IoT)

PLLs

ring oscillators (ROs)

ultralow-power (ULP) frequency synthesizer

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28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

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