Signature of electrothermal transport in 18 nm vertical junctionless gate-all-around nanowire field effect transistors

Addressing temperature hot-spots resulting from self-heating effects (SHE) poses a significant challenge in the design of emerging nanoscale transistors, such as vertical junctionless nanowire field-effect transistors (VNWFETs), due to reduced thermal conductivity. Consequently, electrothermal modeling becomes crucial for a comprehensive understanding of the underlying physical mechanisms governing carrier degradation and thermal conduction in these nanoscale devices. In this study, we present an enhanced drift-diffusion model coupled with nonlocal Guyer-Krumhansl (GK) equations to accurately capture carrier-phonon interactions and explore the electrothermal characteristics of gate-all-around (GAA) VNWFETs. Pulsed current-voltage (I–V) measurements are employed to investigate the performance of a state-of-the-art 18nm VNWFET technology. Furthermore, we report on the influences of both trapping and SHE under high-bias conditions for varying pulse widths. Our findings reveal that optimization of mobility degradation mechanisms allows for improved control over the physical behavior of carrier transport in these emerging technologies. Through careful consideration of these factors, it becomes possible to enhance the overall performance of GAA VNWFETs, particularly in mitigating temperature hot-spots and addressing challenges associated with self-heating effects.< Réduire

Mots clés en anglais

Nanowire field effect transistors

Electrothermal modeling

Pulsed current-voltage measurements

Phonon-carrier interaction

URI

https://oskar-bordeaux.fr/handle/20.500.12278/207723

DOI

http://dx.doi.org/10.1088/1361-6463/ad4716

Projet Européen

Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D

Unités de recherche

IMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218

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