SAINT-GERMAIN, Logan; LE GAL, Bertrand; BALDACCI, Fabien; CRENNE, Jeremie; JEGO, Christophe; LOTY, Sebastien

doi:10.1109/SiPS55645.2022.9919244

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SAINT-GERMAIN, Logan

LE GAL, Bertrand
Laboratoire de l'intégration, du matériau au système [IMS]

BALDACCI, Fabien

Laboratoire Bordelais de Recherche en Informatique [LaBRI]

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2022 IEEE Workshop on Signal Processing Systems (SiPS), 2022 IEEE Workshop on Signal Processing Systems (SiPS), 2022-11-02, Rennes. 2022-10-25p. 1-6

Résumé en anglais

Artificial Intelligence is now ubiquitous as nearly every application domain has found some use for it. The high computational complexity involved in its deployment has led to strong research activity in optimizing its integration in embedded systems. Research works on efficient implementations of CNNs on resource-constrained devices (eg. CPU, FPGA) largely focus on hardware based optimizations such as pruning, quantization or hardware accelerator. However, most performance improvements leading to efficient solutions in terms of memory, complexity and energy are located at the NN topology level, prior to any implementation step. This paper introduces a methodology called ANN2T (Artificial Neural Network to Target) which adapts a pre-trained deep neural network to a designated device with given optimization constraints. ANN2T leverages its included simplifications and/or transformations to progressively modify the deep neural network layers in order to meet the optimization target. Experiment results obtained on microcontroller device show ANN2T produces valuable trade-offs. It achieved up to 33% MACC and 37% memory footprint reductions with no accuracy loss on ResNet-18 topology over the CIFAR-10 dataset. This fully-automated methodology could be generalized to targets such as CPUs, GPUs or FPGAs.< Réduire

Mots clés

Performance evaluation

Deep learning

Quantization (signal)

Network topology

Microcontrollers

Signal processing algorithms

Artificial neural networks

DNN

Machine Learning

Edge AI

TinyML

Embedded Systems

Low Power Devices

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Methodology to Adapt Neural Network on Constrained Device at Topology level

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