SOBAS, Justin; AIRIMITOAIE, Tudor-Bogdan; MARC, Francois

doi:10.1016/j.microrel.2022.114698

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SOBAS, Justin
Laboratoire de l'intégration, du matériau au système [IMS]

AIRIMITOAIE, Tudor-Bogdan

Laboratoire de l'intégration, du matériau au système [IMS]

MARC, Francois

Laboratoire de l'intégration, du matériau au système [IMS]

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Microelectronics Reliability. 2022-11-01, vol. 138, p. 114698

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This article describes the development of a test bench so as to measure the ageing of 16 nm FinFETs used in a Zynq UltraScale+ FPGA from Xilinx. The Ring Oscillator (RO) drift measurement method was chosen and implemented in the setup. However, RO is a circuit sensitive not only to ageing but also to temperature and voltage. In order to mitigate the undesired sensitivity to temperature and voltage, we installed a regulation system to control the temperature and the internal voltage of the FPGA, and we characterised the RO frequency in function of the temperature and the voltage to apply post-measurement compensations. We improved the measurement circuit by using the GPS signal as a time reference. 1000 h test with (TFPGA = 100∘C) and (VFPGA = Vnom + 25%) was performed and results show clear RO frequency drifts lower than 0.1 % measured with an accuracy of 0.9 × 10−4.< Réduire

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Development of a high accuracy and stability test bench for ageing measurement of 16 nm FinFETs based FPGA

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