MAZOUFFRE, O.; LAPOUYADE, H.; BEGUERET, J.B.; CATHELIN, A.; BELOT, D.; HELLMUTH, P.; DEVAL, Y.

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MAZOUFFRE, O.
Laboratoire de l'intégration, du matériau au système [IMS]

LAPOUYADE, H.

BEGUERET, J.B.

Idioma

Communication dans un congrès

Este ítem está publicado en

European Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005, European Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005, 2005-10-03, Paris. 2005-10-03p. 533-536

Resumen en inglés

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL, for ISM band, with a new low power prescaler. This circuit is implemented in a 0.25 mu m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 170 mW and fulfills a 23.7 to 24.9 GHz frequency locking range, while exhibiting a phase noise of -100 dBc/Hz at 100 KHz from the carrier. The simulated PLL unity-gain bandwidth is 36 MHz, with a phase margin of 54 degrees. The PLL uses a new latch-based prescaler (SRO) which exhibits a power dissipation of 0.68 GHz/mW< Leer menos

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Centre d'Études Nucléaires de Bordeaux Gradignan (CENBG)