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Amélioration du processus de vérification des architectures générées à l'aide d'outils de synthèse de haut-niveau
| dc.contributor.advisor | Dallet, Dominique | |
| dc.contributor.advisor | Le Gal, Bertrand | |
| dc.contributor.author | RIBON, Aurélien | |
| dc.contributor.other | Bossuet, Lilian | |
| dc.contributor.other | Casseau, Emmanuel | |
| dc.contributor.other | Jego, Christophe | |
| dc.date | 2012-12-17 | |
| dc.date.accessioned | 2020-12-14T21:15:25Z | |
| dc.date.available | 2020-12-14T21:15:25Z | |
| dc.identifier.uri | http://ori-oai.u-bordeaux1.fr/pdf/2012/RIBON_AURELIEN_2012.pdf | |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/22431 | |
| dc.identifier.nnt | 2012BOR14719 | |
| dc.description.abstract | L'augmentation de la capacité d'intégration des circuits a permis le développement des systèmes de plus en plus complexes. De cette complexité sont nés des besoins conséquents quant aux méthodes de conception et de vérification. Les outils de synthèse de haut-niveau (HLS) sont une des réponses à ces besoins. Les travaux présentés dans cette thèse ont pour cadre l'amélioration du processus de vérification des architectures matérielles synthétisées par HLS. En particulier, ils proposent une méthode pour la transformation des assertions booléennes spécifiées dans la description algorithmique d'une application en moniteurs matériels pour la simulation. Une deuxième méthode est proposée. Elle cible la synthèse automatique d'un gestionnaire d'erreurs matériel dont le rôle est d'archiver les erreurs survenant dans un circuit en fonctionnement réel, ainsi que leurs contextes d'exécution. | |
| dc.description.abstractEn | The fast growing complexity of hardware circuits, during the last three decades, has change devery step of their development cycle. Design methods evolved a lot, and this evolutionwas necessary to cope with an always shorter time-to-market, mainly driven by the internationalcompetition.An increased complexity also means more errors, harder to find corner-cases, and morelong and expensive simulations. The verification of hardware systems requires more andmore resources, and is the main cost factor of the whole development of a circuit. Since thecomplexity of any system increases, the cost of an error undetected until the foundry stepbecame prohibitive. Therefore, the verification process is divided between multiple stepsinvolved at every moment of the design process : comparison of models behavior, simulationof RTL descriptions, formal analysis of algorithms, assertions usage, etc. The verificationmethodologies evolved a lot, in order to follow the progress of design methods. Somemethods like the Assertion-Based Verification became so important that they are nowwidely adopted among the developers community, providing near-source error detection.Thus, the work described here aims at improving the assertion-based verification process,in order to offer a consequent timing improvment to designers. Two contributions aredetailed. The first one deals with the transformation of Boolean assertions found in algorithmicdescriptions into equivalent temporal assertions in the RTL description generatedby high-level synthesis (HLS) methodologies. Therefore, the assertions are usable duringthe simulation process of the generated architectures. The second contribution targets theverification of hardware systems in real-time. It details the synthesis process of a hardwareerror manager, which has to save and serialize the execution context when an error isdetected. Thus, it is easier to understand the cause of an error and to find its source. Theerrors and their contexts are serialized as reports in a memory readable by the system ordirectly by the designer. The behavior of a circuit can be analyzed without requiring anyprobe or integrated logic analyzer. | |
| dc.language.iso | fr | |
| dc.subject | Vérification | |
| dc.subject | Synthèse | |
| dc.subject | Architecture | |
| dc.subject | Assertion | |
| dc.subject | Debug | |
| dc.subject | Erreur | |
| dc.subject | HLS | |
| dc.subject | Moniteur | |
| dc.subject | Rapport | |
| dc.subject.en | Verification | |
| dc.subject.en | Synthesis | |
| dc.subject.en | Architecture | |
| dc.subject.en | Assertion | |
| dc.subject.en | Debug | |
| dc.subject.en | Error | |
| dc.subject.en | HLS | |
| dc.subject.en | Monitor | |
| dc.subject.en | Report | |
| dc.title | Amélioration du processus de vérification des architectures générées à l'aide d'outils de synthèse de haut-niveau | |
| dc.title.en | Improvement of the verification process of architectures generated by high-level synthesis tools | |
| dc.type | Thèses de doctorat | |
| bordeaux.hal.laboratories | Thèses de l'Université de Bordeaux avant 2014 | * |
| bordeaux.hal.laboratories | Laboratoire de l'intégration du matériau au système (Talence, Gironde) | |
| bordeaux.institution | Université de Bordeaux | |
| bordeaux.type.institution | Bordeaux 1 | |
| bordeaux.thesis.discipline | Electronique | |
| bordeaux.ecole.doctorale | École doctorale des sciences physiques et de l’ingénieur (Talence, Gironde) | |
| star.origin.link | https://www.theses.fr/2012BOR14719 | |
| dc.contributor.rapporteur | Anghel, Lorena | |
| dc.contributor.rapporteur | Lagadec, Loïc | |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.title=Am%C3%A9lioration%20du%20processus%20de%20v%C3%A9rification%20des%20architectures%20g%C3%A9n%C3%A9r%C3%A9es%20%C3%A0%20l'aide%20d'outils%20de%20synth%C3%A8se%20de%20haut-&rft.atitle=Am%C3%A9lioration%20du%20processus%20de%20v%C3%A9rification%20des%20architectures%20g%C3%A9n%C3%A9r%C3%A9es%20%C3%A0%20l'aide%20d'outils%20de%20synth%C3%A8se%20de%20haut&rft.au=RIBON,%20Aur%C3%A9lien&rft.genre=unknown |
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