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High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices

dc.rights.licenseopenen_US
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorLE GAL, Bertrand
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorPIGNOLY, Vincent
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorJEGO, Christophe
dc.contributor.editorDESNOS, Karol
dc.contributor.editorPERTUZ, Sergio
dc.date.accessioned2023-05-23T08:55:25Z
dc.date.available2023-05-23T08:55:25Z
dc.date.issued2022-07-30
dc.date.conference2022-06-20
dc.identifier.issn1611-3349en_US
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/182255
dc.description.abstractEnLDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multi-core devices facilitate real-time implementations of digital communication systems, which were previously implemented thanks to dedicated hardware circuits. A lot of works were done over the last decade on the implementation of Gbps decoders on programmable devices. However, these works focus on soft-input LDPC decoding algorithms. But, hard-input LDPC decoders are also required to design and prototype optical-based satellite communication systems. In this article, the first software based implementation of a hard-input multi-Gbps LDPC decoder is detailed. Thanks to different parallelization strategies and deeply optimized SIMD codes, throughputs up to 7.5 Gbps are achieved when 10 Gallager-E iterations are executed onto an INTEL Xeon device.
dc.language.isoENen_US
dc.subjectLDPC
dc.subjectGallager E
dc.subjectMulti-core
dc.subjectSIMD
dc.subjectHigh-throughput
dc.title.enHigh-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices
dc.typeCommunication dans un congrès avec actesen_US
dc.identifier.doi10.1007/978-3-031-12748-9_1en_US
dc.subject.halSciences de l'ingénieur [physics]en_US
bordeaux.page3-15en_US
bordeaux.volume13425en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.conference.title15th International Workshop, DASIP 2022 Budapest, Hungary, June 20-22, 2022, Proceedingsen_US
bordeaux.countryhuen_US
bordeaux.title.proceedingDesign and Architecture for Signal and Image Processingen_US
bordeaux.teamCONCEPTION-CSNen_US
bordeaux.conference.cityBudapesten_US
bordeaux.peerReviewedouien_US
hal.identifierhal-04103371
hal.version1
hal.date.transferred2023-05-23T08:55:27Z
hal.exporttrue
dc.rights.ccPas de Licence CCen_US
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-07-30&rft.volume=13425&rft.spage=3-15&rft.epage=3-15&rft.eissn=1611-3349&rft.issn=1611-3349&rft.au=LE%20GAL,%20Bertrand&PIGNOLY,%20Vincent&JEGO,%20Christophe&rft.genre=proceeding


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