Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
| dc.rights.license | open | en_US |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | REVEIL, Lucas | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MUKHERJEE, Chhandak
IDREF: 228231779 | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MANEUX, Cristell | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | DENG, Marina
IDREF: 184622409 | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MARC, Francois
IDREF: 158656628 | |
| dc.contributor.author | KUMAR, Abhishek | |
| dc.contributor.author | LARRIEU, Guilhem | |
| dc.contributor.author | POITTEVIN, Arnaud | |
| dc.contributor.author | O'CONNOR, Ian | |
| dc.contributor.author | BAUMGARTNER, Oskar | |
| dc.contributor.author | PIRKER, David | |
| dc.date.accessioned | 2023-02-03T15:28:19Z | |
| dc.date.available | 2023-02-03T15:28:19Z | |
| dc.date.issued | 2022-11-08 | |
| dc.date.conference | 2022-10-03 | |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/171866 | |
| dc.description.abstractEn | Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator. | |
| dc.description.sponsorship | Portes logiques élémentaires empillées - ANR-18-CE24-0005 | en_US |
| dc.language.iso | EN | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject.en | Semiconductor device modeling | |
| dc.subject.en | Solid modeling | |
| dc.subject.en | Three-dimensional displays | |
| dc.subject.en | Integrated circuit interconnections | |
| dc.subject.en | Very large scale integration | |
| dc.subject.en | SPICE | |
| dc.subject.en | Inverters | |
| dc.subject.en | Junction-less nanowire transistors | |
| dc.subject.en | 3D logic cells | |
| dc.subject.en | Compact model | |
| dc.subject.en | TCAD simulation | |
| dc.subject.en | Parasitic interconnects | |
| dc.title.en | Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors | |
| dc.type | Communication dans un congrès avec actes | en_US |
| dc.identifier.doi | 10.1109/VLSI-SoC54400.2022.9939576 | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics] | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics]/Electronique | en_US |
| bordeaux.hal.laboratories | IMS : Laboratoire d’Intégration du Matériau au Système - UMR 5218 | en_US |
| bordeaux.institution | Université de Bordeaux | en_US |
| bordeaux.institution | Bordeaux INP | en_US |
| bordeaux.institution | CNRS | en_US |
| bordeaux.conference.title | 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022) | en_US |
| bordeaux.country | gr | en_US |
| bordeaux.title.proceeding | 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022) | en_US |
| bordeaux.conference.city | Patras | en_US |
| bordeaux.peerReviewed | oui | en_US |
| bordeaux.import.source | hal | |
| hal.identifier | hal-03765079 | |
| hal.version | 1 | |
| hal.export | false | |
| workflow.import.source | hal | |
| dc.rights.cc | Pas de Licence CC | en_US |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-11-08&rft.au=REVEIL,%20Lucas&MUKHERJEE,%20Chhandak&MANEUX,%20Cristell&DENG,%20Marina&MARC,%20Francois&rft.genre=proceeding |
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