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Defect Characterization of HfTiOx Gate Dielectrics on SiGe Heterolayers Using Inelastic Tunneling Spectroscopy

dc.rights.licenseopenen_US
dc.contributor.authorMAITI, Partha Pratim
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorMUKHERJEE, Chhandak
IDREF: 228231779
dc.contributor.authorBAG, A.
dc.contributor.authorMALLIK, S.
dc.contributor.authorMAITI, C. K.
dc.date.accessioned2025-10-13T07:13:42Z
dc.date.available2025-10-13T07:13:42Z
dc.date.issued2024-11-16
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/207791
dc.description.abstractEnUltra-thin HfTiOx dielectric films (Ti ~ 26.6%) of thickness ~ 12 nm have been deposited through an RF magnetron co-sputtering process on strained Si0.81Ge0.19 substrates. Samples (HT1, HT2, and HT3) treated by rapid thermal annealing at temperatures ranging from 350 °C to 550 °C were compared with as-deposited samples. From the C–V characteristics of the Au/HfTiOx/p-Si0.81Ge0.19 metal–insulator–semiconductor capacitors, recorded at various frequencies ranging between 50 kHz and 1 MHz, it has been observed that the maximum accumulation capacitance, Cmax , was enhanced to 94 pF after a post-deposition anneal at 350 °C, indicating the formation of a superior interface. The smallest frequency-dependent flat band voltage shift of 0.26 V and the minimum interface trap density (Dit) of 8.62 × 1011 eV−1 cm−2 were both recorded for the HT1 sample. Inelastic tunneling spectroscopy (IETS), a highly sensitive and reliable technique for defect analysis, was then used to evaluate the quality of metal–insulator–semiconductor capacitors. It has been demonstrated that the IETS technique can be used to identify the signatures of different traps. Defect analysis using IETS also helps to understand the microscopic origins of traps and thus can be subsequently used for the estimation of their energy levels, as well as their spatial locations within the dielectric. A comprehensive analysis of the microscopic bonding structures and chemical compositions of hafnium-based high-k gate dielectrics and strained-SiGe interface layers is presented.
dc.language.isoENen_US
dc.subject.enMetal oxide semiconductor
dc.subject.enInelastic tunneling spectroscopy
dc.subject.enHigh-k dielectric
dc.subject.enSiGe
dc.subject.enTrap features
dc.title.enDefect Characterization of HfTiOx Gate Dielectrics on SiGe Heterolayers Using Inelastic Tunneling Spectroscopy
dc.typeArticle de revueen_US
dc.identifier.doi10.1007/s11664-024-11550-7en_US
dc.subject.halSciences de l'ingénieur [physics]en_US
bordeaux.journalJournal of Electronic Materialsen_US
bordeaux.page747-757en_US
bordeaux.volume54en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.issue1en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.teamCIRCUIT DESIGN - M4Cen_US
bordeaux.peerReviewedouien_US
bordeaux.inpressnonen_US
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hal.identifierhal-05310979
hal.version1
hal.date.transferred2025-10-13T07:13:45Z
hal.popularnonen_US
hal.audienceInternationaleen_US
hal.exporttrue
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dc.rights.ccPas de Licence CCen_US
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