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dc.rights.licenseopenen_US
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorREZGUI, Houssem
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorWANG, Yifan
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorMUKHERJEE, Chhandak
IDREF: 228231779
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorDENG, Marina
IDREF: 184622409
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorMANEUX, Cristell
IDREF: 135213584
dc.date.accessioned2025-10-06T10:14:23Z
dc.date.available2025-10-06T10:14:23Z
dc.date.issued2024-10-17
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/207723
dc.description.abstractEnAddressing temperature hot-spots resulting from self-heating effects (SHE) poses a significant challenge in the design of emerging nanoscale transistors, such as vertical junctionless nanowire field-effect transistors (VNWFETs), due to reduced thermal conductivity. Consequently, electrothermal modeling becomes crucial for a comprehensive understanding of the underlying physical mechanisms governing carrier degradation and thermal conduction in these nanoscale devices. In this study, we present an enhanced drift-diffusion model coupled with nonlocal Guyer-Krumhansl (GK) equations to accurately capture carrier-phonon interactions and explore the electrothermal characteristics of gate-all-around (GAA) VNWFETs. Pulsed current-voltage (I–V) measurements are employed to investigate the performance of a state-of-the-art 18nm VNWFET technology. Furthermore, we report on the influences of both trapping and SHE under high-bias conditions for varying pulse widths. Our findings reveal that optimization of mobility degradation mechanisms allows for improved control over the physical behavior of carrier transport in these emerging technologies. Through careful consideration of these factors, it becomes possible to enhance the overall performance of GAA VNWFETs, particularly in mitigating temperature hot-spots and addressing challenges associated with self-heating effects.
dc.language.isoENen_US
dc.subject.enNanowire field effect transistors
dc.subject.enElectrothermal modeling
dc.subject.enPulsed current-voltage measurements
dc.subject.enPhonon-carrier interaction
dc.titleSignature of electrothermal transport in 18 nm vertical junctionless gate-all-around nanowire field effect transistors
dc.typeArticle de revueen_US
dc.identifier.doi10.1088/1361-6463/ad4716en_US
dc.subject.halSciences de l'ingénieur [physics]en_US
dc.description.sponsorshipEuropeFerroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3Den_US
bordeaux.journalJournal of Physics D: Applied Physicsen_US
bordeaux.page025110en_US
bordeaux.volume58en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.issue2en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.teamCIRCUIT DESIGN - M4Cen_US
bordeaux.peerReviewedouien_US
bordeaux.inpressnonen_US
bordeaux.import.sourcecrossref
hal.popularnonen_US
hal.audienceInternationaleen_US
hal.exportfalse
workflow.import.sourcecrossref
dc.rights.ccPas de Licence CCen_US
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.title=Signature%20of%20electrothermal%20transport%20in%2018%20nm%20vertical%20junctionless%20gate-all-around%20nanowire%20field%20effect%20transistors&rft.atitle=Signature%20of%20electrothermal%20transport%20in%2018%20nm%20vertical%20junctionless%20gate-all-around%20nanowire%20field%20effect%20transistors&rft.jtitle=Journal%20of%20Physics%20D:%20Applied%20Physics&rft.date=2024-10-17&rft.volume=58&rft.issue=2&rft.spage=025110&rft.epage=025110&rft.au=REZGUI,%20Houssem&WANG,%20Yifan&MUKHERJEE,%20Chhandak&DENG,%20Marina&MANEUX,%20Cristell&rft.genre=article


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