A unified runtime system for heterogeneous multicore architectures
| hal.structure.identifier | Laboratoire Bordelais de Recherche en Informatique [LaBRI] | |
| hal.structure.identifier | Efficient runtime systems for parallel architectures [RUNTIME] | |
| dc.contributor.author | AUGONNET, Cédric | |
| hal.structure.identifier | Laboratoire Bordelais de Recherche en Informatique [LaBRI] | |
| hal.structure.identifier | Efficient runtime systems for parallel architectures [RUNTIME] | |
| dc.contributor.author | NAMYST, Raymond | |
| dc.date.accessioned | 2024-04-15T09:54:18Z | |
| dc.date.available | 2024-04-15T09:54:18Z | |
| dc.date.issued | 2008 | |
| dc.date.conference | 2008-08-26 | |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/198661 | |
| dc.description.abstractEn | Approaching the theoretical performance of heterogeneous multicore architectures, equipped with specialized accelerators, is a challenging issue. Unlike regular CPUs that can transparently access the whole global memory address range, accelerators usually embed local memory on which they perform all their computations using a specific instruction set. While many research efforts have been devoted to offloading parts of a program over such coprocessors, the real challenge is to find a programming model providing a unified view of all available computing units. In this paper, we present an original runtime system providing a high-level, unified execution model allowing seamless execution of tasks over the underlying heterogeneous hardware. The runtime is based on a hierarchical memory management facility and on a codelet scheduler. We demonstrate the efficiency of our solution with a LU decomposition for both homogeneous (3.8 speedup on 4 cores) and heterogeneous machines (95% efficiency). We also show that a "granularity aware" scheduling can improve execution time by 35%. | |
| dc.language.iso | en | |
| dc.title.en | A unified runtime system for heterogeneous multicore architectures | |
| dc.type | Communication dans un congrès | |
| dc.subject.hal | Informatique [cs]/Système d'exploitation [cs.OS] | |
| bordeaux.hal.laboratories | Laboratoire Bordelais de Recherche en Informatique (LaBRI) - UMR 5800 | * |
| bordeaux.institution | Université de Bordeaux | |
| bordeaux.institution | Bordeaux INP | |
| bordeaux.institution | CNRS | |
| bordeaux.conference.title | 2nd Workshop on Highly Parallel Processing on a Chip (HPPC 2008) | |
| bordeaux.country | ES | |
| bordeaux.conference.city | Las Palmas de Gran Canaria | |
| bordeaux.peerReviewed | oui | |
| hal.identifier | inria-00326917 | |
| hal.version | 1 | |
| hal.invited | non | |
| hal.proceedings | oui | |
| hal.popular | non | |
| hal.audience | Internationale | |
| hal.origin.link | https://hal.archives-ouvertes.fr//inria-00326917v1 | |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2008&rft.au=AUGONNET,%20C%C3%A9dric&NAMYST,%20Raymond&rft.genre=unknown |
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