A NUMA Aware Scheduler for a Parallel Sparse Direct Solver
| hal.structure.identifier | Laboratoire Bordelais de Recherche en Informatique [LaBRI] | |
| hal.structure.identifier | Algorithms and high performance computing for grand challenge applications [SCALAPPLIX] | |
| dc.contributor.author | FAVERGE, Mathieu | |
| hal.structure.identifier | Laboratoire Bordelais de Recherche en Informatique [LaBRI] | |
| hal.structure.identifier | Algorithms and high performance computing for grand challenge applications [SCALAPPLIX] | |
| dc.contributor.author | RAMET, Pierre | |
| dc.date.accessioned | 2024-04-15T09:50:14Z | |
| dc.date.available | 2024-04-15T09:50:14Z | |
| dc.date.issued | 2008-12-18 | |
| dc.date.conference | 2009-02-04 | |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/198321 | |
| dc.description.abstractEn | Over the past few years, parallel sparse direct solvers have made significant progress. They are now able to solve efficiently real-life three-dimensional problems with several millions of equations. Nevertheless, the need of a large amount of memory is often a bottleneck in these methods. The authors have proposed an hybrid MPI-thread implementation of a direct solver that is well suited for SMP nodes or modern multi-core architectures. Modern multi-processing architectures are commonly based on shared memory systems with a NUMA behavior. These computers are composed of several chip-sets including one or several cores associated to a memory bank. Such an architecture implies hierarchical memory access times from a given core to the different memory banks which do not exist on SMP nodes. Thus, the main data structure of our targeted application have been modified to be more suitable for NUMA architectures. We also introduce a simple way of dynamically schedule an application based on a dependency tree while taking into account NUMA effects. Results obtained with these modifications are illustrated by showing performances of the PaStiX solver on different platforms and matrices. | |
| dc.description.sponsorship | Adaptation et Optimisation des Performances Applicatives sur architectures NUMA. Etude et Mise en Œuvre sur des Applications en SISmologie. - ANR-05-CIGC-0002 | |
| dc.language.iso | en | |
| dc.source.title | Proc. MMMC2008 | |
| dc.subject.en | http://www.labri.fr/~ramet/restricted/i3m.pdf.gz | |
| dc.title.en | A NUMA Aware Scheduler for a Parallel Sparse Direct Solver | |
| dc.type | Communication dans un congrès | |
| dc.subject.hal | Informatique [cs]/Calcul parallèle, distribué et partagé [cs.DC] | |
| bordeaux.page | 5p. | |
| bordeaux.hal.laboratories | Laboratoire Bordelais de Recherche en Informatique (LaBRI) - UMR 5800 | * |
| bordeaux.institution | Université de Bordeaux | |
| bordeaux.institution | Bordeaux INP | |
| bordeaux.institution | CNRS | |
| bordeaux.conference.title | Workshop on Massively Multiprocessor and Multicore Computers | |
| bordeaux.country | FR | |
| bordeaux.title.proceeding | Proc. MMMC2008 | |
| bordeaux.conference.city | Rocquencourt | |
| bordeaux.peerReviewed | oui | |
| hal.identifier | inria-00416502 | |
| hal.version | 1 | |
| hal.invited | non | |
| hal.proceedings | oui | |
| hal.conference.organizer | INRIA | |
| hal.conference.end | 2009-02-05 | |
| hal.popular | non | |
| hal.audience | Internationale | |
| hal.origin.link | https://hal.archives-ouvertes.fr//inria-00416502v1 | |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.btitle=Proc.%20MMMC2008&rft.date=2008-12-18&rft.spage=5p.&rft.epage=5p.&rft.au=FAVERGE,%20Mathieu&RAMET,%20Pierre&rft.genre=unknown |
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