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hal.structure.identifierLaboratoire Bordelais de Recherche en Informatique [LaBRI]
hal.structure.identifierAlgorithms and high performance computing for grand challenge applications [SCALAPPLIX]
dc.contributor.authorFAVERGE, Mathieu
hal.structure.identifierLaboratoire Bordelais de Recherche en Informatique [LaBRI]
hal.structure.identifierAlgorithms and high performance computing for grand challenge applications [SCALAPPLIX]
dc.contributor.authorRAMET, Pierre
dc.date.accessioned2024-04-15T09:50:14Z
dc.date.available2024-04-15T09:50:14Z
dc.date.issued2008-12-18
dc.date.conference2009-02-04
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/198321
dc.description.abstractEnOver the past few years, parallel sparse direct solvers have made significant progress. They are now able to solve efficiently real-life three-dimensional problems with several millions of equations. Nevertheless, the need of a large amount of memory is often a bottleneck in these methods. The authors have proposed an hybrid MPI-thread implementation of a direct solver that is well suited for SMP nodes or modern multi-core architectures. Modern multi-processing architectures are commonly based on shared memory systems with a NUMA behavior. These computers are composed of several chip-sets including one or several cores associated to a memory bank. Such an architecture implies hierarchical memory access times from a given core to the different memory banks which do not exist on SMP nodes. Thus, the main data structure of our targeted application have been modified to be more suitable for NUMA architectures. We also introduce a simple way of dynamically schedule an application based on a dependency tree while taking into account NUMA effects. Results obtained with these modifications are illustrated by showing performances of the PaStiX solver on different platforms and matrices.
dc.description.sponsorshipAdaptation et Optimisation des Performances Applicatives sur architectures NUMA. Etude et Mise en Œuvre sur des Applications en SISmologie. - ANR-05-CIGC-0002
dc.language.isoen
dc.source.titleProc. MMMC2008
dc.subject.enhttp://www.labri.fr/~ramet/restricted/i3m.pdf.gz
dc.title.enA NUMA Aware Scheduler for a Parallel Sparse Direct Solver
dc.typeCommunication dans un congrès
dc.subject.halInformatique [cs]/Calcul parallèle, distribué et partagé [cs.DC]
bordeaux.page5p.
bordeaux.hal.laboratoriesLaboratoire Bordelais de Recherche en Informatique (LaBRI) - UMR 5800*
bordeaux.institutionUniversité de Bordeaux
bordeaux.institutionBordeaux INP
bordeaux.institutionCNRS
bordeaux.conference.titleWorkshop on Massively Multiprocessor and Multicore Computers
bordeaux.countryFR
bordeaux.title.proceedingProc. MMMC2008
bordeaux.conference.cityRocquencourt
bordeaux.peerReviewedoui
hal.identifierinria-00416502
hal.version1
hal.invitednon
hal.proceedingsoui
hal.conference.organizerINRIA
hal.conference.end2009-02-05
hal.popularnon
hal.audienceInternationale
hal.origin.linkhttps://hal.archives-ouvertes.fr//inria-00416502v1
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.btitle=Proc.%20MMMC2008&rft.date=2008-12-18&rft.spage=5p.&rft.epage=5p.&rft.au=FAVERGE,%20Mathieu&RAMET,%20Pierre&rft.genre=unknown


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