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dc.rights.licenseopenen_US
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorHOSSAIN, Md Sazzad
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorMOREIRA, Mateus Bernardino
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorSANDREZ, Francois
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorRIVET, Francois
IDREF: 135485576
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorLAPUYADE, Herve
IDREF: 120393336
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorDEVAL, Yann
dc.date.accessioned2023-12-12T09:36:37Z
dc.date.available2023-05-09T10:12:49Z
dc.date.available2023-12-12T09:36:37Z
dc.date.issued2022-06-08
dc.date.conference2022-03-01
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/173667.2
dc.description.abstractEnIn this work, Integer N frequency dividers are designed in a dual loop PLL circuit which is applicable at reference frequency 40.92MHz and 400MHz and for a feedback input frequency 0.8GHz-6.3GHz with very low power consumption and small die area. A fast and energy-efficient True Single Phase Clock (TSPC) D-Flip Flops with a controlled pre-charger circuit has been explained for designing reference and feedback frequency dividers (sequentially 4-bit De-Counter and 8-bit De-Counter). The phase noise (PN) of the dividers always remains at −130dBc/Hz at 1MHz offset. The circuit was designed and implemented in 28nm FDSOI technology and the divider's maximum current consumption is 208μA at 1 V.
dc.language.isoENen_US
dc.subjectPhase noise
dc.subjectFrequency locked loops
dc.subjectPower demand
dc.subjectCircuits and systems
dc.subjectSilicon-on-insulator
dc.subjectFrequency conversion
dc.subjectEnergy efficiency
dc.subjectClocks
dc.subjectFlip-flops
dc.subjectFrequency dividers
dc.subjectLow-power electronics
dc.subjectPhase locked loops
dc.subjectPhase noise
dc.subjectSilicon-on-insulator
dc.subjectTSPC
dc.subjectFDSOI
dc.subjectDrequency dividers
dc.subjectDe-counter
dc.subjectPhase noise
dc.title.enLow Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology
dc.typeCommunication dans un congrèsen_US
dc.identifier.doi10.1109/LASCAS53948.2022.9789073en_US
dc.subject.halSciences de l'ingénieur [physics]/Micro et nanotechnologies/Microélectroniqueen_US
dc.description.sponsorshipEuropeOpportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm nodeen_US
bordeaux.page1-4en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.conference.title2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)en_US
bordeaux.countryclen_US
bordeaux.title.proceeding2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)en_US
bordeaux.teamBIOELECTRONIQUE-IAen_US
bordeaux.teamCONCEPTION-CASen_US
bordeaux.conference.cityPuerto Varasen_US
hal.identifierhal-04337331
hal.version1
hal.date.transferred2023-12-12T09:36:39Z
hal.invitedouien_US
hal.proceedingsouien_US
hal.conference.end2022-03-04
hal.popularnonen_US
hal.audienceInternationaleen_US
hal.exporttrue
dc.rights.ccPas de Licence CCen_US
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-06-08&rft.spage=1-4&rft.epage=1-4&rft.au=HOSSAIN,%20Md%20Sazzad&MOREIRA,%20Mateus%20Bernardino&SANDREZ,%20Francois&RIVET,%20Francois&LAPUYADE,%20Herve&rft.genre=unknown


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