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New design optimization methodologies of aeronautic boards embedding SERDES up to 40 Gbps: tradeoff between performance and cost

dc.rights.licenseopenen_US
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
hal.structure.identifierThales AVS France SAS
dc.contributor.authorLE BIHAN, Soazig
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorDUBOIS, Tristan
IDREF: 139527613
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorBEGUERET, Jean Baptiste
IDREF: 117735418
hal.structure.identifierThales AVS France SAS
dc.contributor.authorGATTI, Marc
hal.structure.identifierThales AVS France SAS
dc.contributor.authorABBAZI, Adil El
dc.date.accessioned2025-03-27T14:53:23Z
dc.date.available2025-03-27T14:53:23Z
dc.date.issued2023-11-10
dc.date.conference2023-10-01
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/205726
dc.description.abstractEnThe evolution of printed circuit technologies over the years has enabled them to acquire better density and finer engraving. Data rates and clock speeds increase with reduced switching times and power consumption over ever-smaller spaces.To ensure that these evolutions do not affect signal integrity, high-speed signal quality simulations and measurements are required. Simulation can predict potential weaknesses before manufacturing, while measurements help identify design failures and build confidence in simulation results for future board designs.Analyzing and optimizing every potential discontinuity has become an essential part of signal integrity. Factors that affect signal quality include signal attenuation, impedance matching, crosstalk, and jitter. Signal attenuation occurs due to dielectric and conductive losses. Signal integrity (SI) analysis should no longer consider the dielectric as homogeneous and the copper as a flat surface. It must take into account its actual structure within the PCB and its anisotropic and frequency-dependent properties.These effects will be studied for serial high-speed links (Serdes with PCIe and Ethernet) up to 40Gpbs.
dc.language.isoENen_US
dc.publisherIEEEen_US
dc.subject.enSignal integrity
dc.subject.enHigh-speed links
dc.subject.enSerDes
dc.subject.enModels
dc.subject.enRoughness
dc.subject.enGlass weave skew
dc.subject.enOptimization
dc.subject.enEqualization
dc.title.enNew design optimization methodologies of aeronautic boards embedding SERDES up to 40 Gbps: tradeoff between performance and cost
dc.typeCommunication dans un congrèsen_US
dc.identifier.doi10.1109/dasc58513.2023.10311261en_US
dc.subject.halSciences de l'ingénieur [physics]en_US
bordeaux.page1-6en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.conference.title2023 IEEE/AIAA 42nd Digital Avionics Systems Conference (DASC)en_US
bordeaux.countryesen_US
bordeaux.title.proceedingDASC 2023 Conference proceedingsen_US
bordeaux.teamRELIABILITYen_US
bordeaux.teamCIRCUIT DESIGNen_US
bordeaux.conference.cityBarceloneen_US
bordeaux.import.sourcecrossref
hal.identifierhal-05008948
hal.version1
hal.date.transferred2025-03-27T14:53:25Z
hal.proceedingsouien_US
hal.conference.end2024-10-05
hal.popularnonen_US
hal.audienceInternationaleen_US
hal.exporttrue
workflow.import.sourcecrossref
dc.rights.ccPas de Licence CCen_US
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2023-11-10&rft.spage=1-6&rft.epage=1-6&rft.au=LE%20BIHAN,%20Soazig&DUBOIS,%20Tristan&BEGUERET,%20Jean%20Baptiste&GATTI,%20Marc&ABBAZI,%20Adil%20El&rft.genre=unknown


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