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Flexible design methodology for spike encoding implementation on FPGA

dc.rights.licenseopenen_US
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorGILLET, Clemence
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorVINCENT, Adrien F.
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorLE GAL, Bertrand
hal.structure.identifierLaboratoire de l'intégration, du matériau au système [IMS]
dc.contributor.authorSAÏGHI, Sylvain
dc.date.accessioned2024-05-07T11:28:13Z
dc.date.available2024-05-07T11:28:13Z
dc.date.issued2022-10
dc.date.conference2022-10-13
dc.identifier.issn2473-2001en_US
dc.identifier.urihttps://oskar-bordeaux.fr/handle/20.500.12278/199699
dc.description.abstractEnSpiking Neural Networks (SNNs) are promising candidates for low power and low latency embedded artificial intelligence, e.g., for edge computing. There is, however, a lack of naturally event-based sensors that could directly feed those networks, except for a few specialized flagship examples like neuromorphic retinas. Using conventional sensors in conjunction with SNNs requires to encode their outputs into spikes, which can be detrimental to energy consumption or latency when performed in software. Spike-encoding algorithms have been studied within specific contexts in the literature but are often limited to a software implementation. Here we introduce a flexible design methodology for implementing a generalized version of such a spike-encoder on Field Programmable Gate Array (FPGA). Our approach relies on High-Level Synthesis, which allows to quickly evaluate different hardware architectures to tailor the solution to the application needs. This work could accelerate the development of lower power and lower latency smart sensors by combining conventional, possibly off-the-shelf, sensors with hardware SNNs.
dc.language.isoENen_US
dc.subjectEnergy consumption
dc.subjectDesign methodology
dc.subjectSoftware algorithms
dc.subjectComputer architecture
dc.subjectHardware
dc.subjectSoftware
dc.subjectEncoding
dc.subjectSpiking neural networks
dc.subjectData encoding
dc.subjectHigh level synthesis
dc.subjectSpike sorting
dc.subjectEdge computing
dc.title.enFlexible design methodology for spike encoding implementation on FPGA
dc.typeCommunication dans un congrèsen_US
dc.identifier.doi10.1109/BioCAS54905.2022.9948601en_US
dc.subject.halSciences de l'ingénieur [physics]en_US
bordeaux.page379-383en_US
bordeaux.hal.laboratoriesIMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218en_US
bordeaux.institutionUniversité de Bordeauxen_US
bordeaux.institutionBordeaux INPen_US
bordeaux.institutionCNRSen_US
bordeaux.conference.title2022 IEEE Biomedical Circuits and Systems Conference (BioCAS)en_US
bordeaux.countrytwen_US
bordeaux.title.proceeding2022 IEEE Biomedical Circuits and Systems Conference (BioCAS)en_US
bordeaux.teamBIOELECTRONICS-IAen_US
bordeaux.teamCIRCUIT DESIGN-CSNen_US
bordeaux.conference.cityTaipeien_US
hal.identifierhal-04570859
hal.version1
hal.date.transferred2024-05-07T11:28:15Z
hal.invitedouien_US
hal.proceedingsouien_US
hal.conference.end2022-10-15
hal.popularnonen_US
hal.audienceInternationaleen_US
hal.exporttrue
dc.rights.ccPas de Licence CCen_US
bordeaux.COinSctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-10&rft.spage=379-383&rft.epage=379-383&rft.eissn=2473-2001&rft.issn=2473-2001&rft.au=GILLET,%20Clemence&VINCENT,%20Adrien%20F.&LE%20GAL,%20Bertrand&SA%C3%8FGHI,%20Sylvain&rft.genre=unknown


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