0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI

Abstract

This paper presents the design and measurement results of an sub-half-mW frequency synthesizer, composed of a multiplying delay-locked loop (MDLL), which reduces the phase noise of a standard ring oscillator. The proposed circuit takes advantage of the low-jitter and high loop bandwidth characteristic of the MDLLs, and has the particular feature of being able to lock to any external reference frequency between 50 and 100 MHz. It is known from the previous state-of-theart implementations that the reference spur degrades the output spectrum. In this work, an ultra-low-power spur reduction circuit is proposed to improve the spectral purity of the output spectrum, achieving -47.2dBc of spur rejection, measured for 10 chips. For 456 μW of power consumption, 2.5 ps of RMS jitter, the proposed solution presents a Figure of merit (FoM) of -235dB, being suitable for ultra-low-power IoT applications.