A 5G 65-nm PD-SOI CMOS 23.2-to-28.8 GHz Low-Jitter Quadrature-Coupled Injection-Locked Digitally-Controlled Oscillator

Abstract

A low-phase-noise mm-W low-power quadrature differentially injection-locked digitally-controlled oscillator (QILDCO) is presented. This work adopts a differential injection to enable a trade-off between phase noise performance and power consumption. Switched-capacitor banks and active devices are integrated inside the inductor loop to reduce the active area. The total active area is 0.109 mm 2 including harmonic extractors and buffers (excluding I/O pads). The proposed oscillator is supporting two 5G mm-W bands below 30 GHz with a tuning range of 21.3%. The prototype has been implemented in 65-nm Partially-Depleted SOI (PD-SOI) CMOS process. It achieves best state-of-the-art jitter of 25.6 fs while consuming 22 mW from a 1 V supply voltage.