A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology
Langue
EN
Communication dans un congrès
Ce document a été publié dans
2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024-11-18, Nancy. 2025-01-28p. 1-4
IEEE
Résumé en anglais
This paper discusses the development of a new topology voltage reference in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The voltage reference described in this paper is based on threshold voltage subtraction ...Lire la suite >
Mots clés
Temperature dependence
Temperature distribution
Subtraction techniques
Layout
Silicon-on-insulator
Aerospace electronics
Threshold voltage
Topology
Transistors
Electronic circuits
Voltage reference
PTAT
CTAT
Back-Gate biasing
Thermal dependency
FD-SOI