Efficient Software and Hardware Implementations of a QCSP Communication System
| dc.rights.license | open | en_US |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | MONIERE, Camille | |
| hal.structure.identifier | Laboratoire de l'intégration, du matériau au système [IMS] | |
| dc.contributor.author | LE GAL, Bertrand | |
| dc.contributor.author | BOUTILLON, Emmanuel | |
| dc.contributor.editor | DESNOS, Karol | |
| dc.contributor.editor | PERTUZ, Sergio | |
| dc.date.accessioned | 2023-05-23T07:55:13Z | |
| dc.date.available | 2023-05-23T07:55:13Z | |
| dc.date.issued | 2022-07-30 | |
| dc.date.conference | 2022-06-20 | |
| dc.identifier.issn | 1611-3349 | en_US |
| dc.identifier.uri | https://oskar-bordeaux.fr/handle/20.500.12278/182254 | |
| dc.description.abstractEn | In wireless communications, frame detection and synchronization are usually performed using a preamble, consuming bandwidth and resources that are not negligible for small packets. Recently, a new kind of preamble-free frame called Quasi Cyclic Small Packet (QCSP) have been proposed. This paper studies the implementation of QCSP transmission, both at the transmitter side and the receiver side. For the latter, only detection, the most consuming task, is considered. Different parallelism levels and implementation strategies are detailed for both software and hardware implementations. Several trade-offs between throughput and resource usage are also discussed. Finally, the paper demonstrates that the emission/reception process of a QCSP frame is feasible at low hardware cost, which make the QCSP frame very attractive for Low Power Wide Area Networks (LPWAN). | |
| dc.language.iso | EN | en_US |
| dc.subject | Real-Time Implementation | |
| dc.subject | CCSK | |
| dc.subject | Small Packets | |
| dc.subject | Hardware | |
| dc.subject | Software | |
| dc.subject | Low Power Wide Area Network | |
| dc.title.en | Efficient Software and Hardware Implementations of a QCSP Communication System | |
| dc.type | Communication dans un congrès avec actes | en_US |
| dc.identifier.doi | 10.1007/978-3-031-12748-9_3 | en_US |
| dc.subject.hal | Sciences de l'ingénieur [physics] | en_US |
| bordeaux.page | 29-41 | en_US |
| bordeaux.volume | 13425 | en_US |
| bordeaux.hal.laboratories | IMS : Laboratoire de l'Intégration du Matériau au Système - UMR 5218 | en_US |
| bordeaux.institution | Université de Bordeaux | en_US |
| bordeaux.institution | Bordeaux INP | en_US |
| bordeaux.institution | CNRS | en_US |
| bordeaux.conference.title | 15th International Workshop, DASIP 2022 Budapest, Hungary, June 20-22, 2022, Proceedings | en_US |
| bordeaux.country | hu | en_US |
| bordeaux.title.proceeding | Design and Architecture for Signal and Image Processing | en_US |
| bordeaux.team | CONCEPTION-CSN | en_US |
| bordeaux.conference.city | Budapest | en_US |
| bordeaux.peerReviewed | oui | en_US |
| hal.identifier | hal-04103277 | |
| hal.version | 1 | |
| hal.date.transferred | 2023-05-23T07:55:15Z | |
| hal.export | true | |
| dc.rights.cc | Pas de Licence CC | en_US |
| bordeaux.COinS | ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.date=2022-07-30&rft.volume=13425&rft.spage=29-41&rft.epage=29-41&rft.eissn=1611-3349&rft.issn=1611-3349&rft.au=MONIERE,%20Camille&LE%20GAL,%20Bertrand&BOUTILLON,%20Emmanuel&rft.genre=proceeding |
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