Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter
Language
en
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Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter, Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter, 2011-12-11, BEYROUTH. 2011-12-11p. 22-26
English Abstract
This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. Our circuit has been ...Read more >
This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. Our circuit has been fabricated with the 65nm technology from STMicroelectronics. The post-layout simulations show a Figure of Merit (FoM) of 11.36pJ/conv.step and a power consumption of 480mW at Nyquist sampling condition. The ongoing tests will soon verify these predictionsRead less <
Origin
Hal imported